Current high-integrity avionics systems such as fly-by-wire systems typically use computers having multiple lanes of computation. Each lane of computation may be designed to be fault independent of the other lanes of computation, such that faults may be detected and/or mitigated to minimize failure of the overall system. In such systems, a commercial-off-the-shelf (COTS) processor may be used in each lane of computation, where the COTS processor in each lane of computation may be dissimilar from the respective COTS processor(s) in the other lane(s) of computation. Dissimilar processors may be used in fly-by-wire systems to minimize errors in processor output due to processor design.
The data input to the processors may be synchronized such that the processors in the multiple lanes of computation may perform the same computations on the same data inputs and may, therefore, output the same (or substantially the same) values. The outputs from the dissimilar processors of the multiple lanes of computation may be cross-compared to detect failures and/or errors. However, because not all lanes of computation may operate at the same speed, and because the input data may be accessed using relatively slow peripheral buses, synchronizing the access of the processors to the input data on a transaction-wire basis may require relatively faster lanes of computation to wait for relatively slower lanes of computation to be ready to access the data, resulting in decreased processing performance. Further, such systems may accommodate only a single processor in each lane of computation, since using multiple processors in a lane of computation may result in improper data transfer due to the processors accessing input data in different order.
What is needed, then, are systems and methods for synchronizing access of input data by multiple processors at substantially the same time in order to minimize synchronized input waiting times, resulting in an improved performance, and minimize improper data transfer.